| Integrated Circuit Test Engineering 发表于：08-08-20 最后更新时间：08-10-03 所属论坛：半导体测试 评论(8) | 完整回复 | 提交评论 | 打印此页 共9项,第1/1页 |
又见飞刀 普通会员 积分：67 |
Contents Abbreviations ......................................................................................................xxv 1 Introduction to Integrated Circuit Test Engineering.....................................1 1.1 Introduction...............................................................................................1 1.2 The Rule of Ten ........................................................................................3 1.3 The Evolution of Test Engineering ...........................................................3 1.4 Test Engineer Activities............................................................................4 1.5 Device Testing ..........................................................................................7 1.6 Production Test: ATE Systems .................................................................8 1.7 Technology Trends .................................................................................10 1.8 International Technology Roadmap for Semiconductors (ITRS)............11 1.9 Computer Aided Test ..............................................................................12 1.10 Virtual Test .............................................................................................12 1.11 Moore’s Law...........................................................................................12 1.12 Rent’s Rule..............................................................................................13 1.13 Benchmark Circuits.................................................................................14 1.14 DfX .........................................................................................................14 1.15 Summary .................................................................................................14 1.16 References ..............................................................................................15 2 Fabrication Processes for Integrated Circuits ..............................................17 2.1 Introduction.............................................................................................17 2.2 Technology Nodes ..................................................................................19 2.3 Wafer Size...............................................................................................20 2.4 Bipolar Technology.................................................................................21 2.5 Complementary Metal Oxide Semiconductor (CMOS) Technology ......22 2.6 BiCMOS Technology .............................................................................29 2.7 SiGe BiCMOS Technology.....................................................................29 2.8 Gallium Arsenide (GaAs) Technology ...................................................29 2.9 Memory Processes ..................................................................................29 2.10 Packaging................................................................................................30 2.11 Die Bonding ............................................................................................31 xvii xviii Table of Contents 2.12 Multi-Chip Modules................................................................................32 2.13 Foundry Services.....................................................................................34 2.14 Process Variations...................................................................................35 2.15 Electromigration......................................................................................35 2.16 Future Directions.....................................................................................35 2.17 Summary .................................................................................................36 2.18 References...............................................................................................37 Exercises ...........................................................................................................38 3 Digital Logic Test ............................................................................................41 3.1 Introduction.............................................................................................41 3.2 Logic Families.........................................................................................44 3.3 Digital Logic ICs.....................................................................................45 3.4 Programmable Logic...............................................................................46 3.5 Basic Logic Gates ...................................................................................48 3.6 Hardware Description Languages ...........................................................49 3.7 Digital Circuit and System Design Flow.................................................50 3.8 Number Systems .....................................................................................52 3.9 CMOS Inverter........................................................................................53 3.10 Latch-Up .................................................................................................61 3.11 Introduction to Digital Logic Test...........................................................62 3.12 Fault Models ...........................................................................................66 3.12.1 Stuck-At-Fault ...........................................................................66 3.12.2 Bridging Fault............................................................................67 3.12.3 Delay Fault ................................................................................69 3.12.4 Memory Fault ............................................................................69 3.12.5 Stuck-Open and Stuck Short Faults ...........................................70 3.12.6 IDDQ Fault...................................................................................70 3.13 Combinational Logic Test.......................................................................74 3.13.1 Introduction ...............................................................................74 3.13.2 Test Pattern Generation .............................................................74 3.13.3 Non-Detectable Faults Due to Circuit Redundancy...................75 3.13.4 Fan-out and Reconvergence ......................................................76 3.13.5 Local and Global Feedback .......................................................77 3.13.6 Multiple Faults and Fault Masking............................................77 3.13.7 Limitations of Fault Models ......................................................77 3.13.8 The Fault Matrix........................................................................77 3.14 Sequential Logic Test..............................................................................81 3.14.1 Introduction ...............................................................................81 3.14.2 D-Type Bistable.........................................................................82 3.14.3 Example Circuits .......................................................................83 3.15 DfT and BIST Overview.........................................................................85 3.16 Future Directions.....................................................................................86 3.17 Summary .................................................................................................88 3.18 References...............................................................................................88 Exercises ...........................................................................................................91 Table of Contents xix 4 Memory Test....................................................................................................95 4.1 Introduction.............................................................................................95 4.1.1 Memory Overview.....................................................................95 4.1.2 Read Only Memory (ROM).......................................................98 4.1.3 Random Access Memory (RAM)..............................................98 4.2 SRAM Structure......................................................................................99 4.3 DRAM Structure ...................................................................................102 4.4 ROM structure.......................................................................................104 4.5 Fault Modelling in Memory ..................................................................105 4.6 RAM Test Algorithms ..........................................................................107 4.6.1 Introduction .............................................................................107 4.6.2 Notation ...................................................................................108 4.6.3 RAM Test Algorithms .............................................................109 4.7 Memory Access for Test .......................................................................112 4.8 Memory BIST .......................................................................................113 4.9 ROM Test .............................................................................................115 4.10 Future Directions...................................................................................115 4.11 Summary ...............................................................................................117 4.12 References.............................................................................................117 Exercises .........................................................................................................119 5 Analogue Test ................................................................................................123 5.1 Introduction...........................................................................................123 5.2 Analogue Circuit Overview ..................................................................126 5.3 Measuring Analogue Parameters ..........................................................130 5.4 Coherent Sampling ...............................................................................133 5.5 Functional vs Structural Test ................................................................136 5.6 Fault Modelling in Analogue ................................................................136 5.7 Future Directions...................................................................................137 5.8 Summary ...............................................................................................138 5.9 References.............................................................................................139 Exercises .........................................................................................................141 6 Mixed-Signal Test..........................................................................................143 6.1 Introduction...........................................................................................143 6.2 Mixed-Signal Circuit Test Overview ....................................................145 6.3 Fault Modelling in Mixed-Signal Circuits ............................................147 6.4 DAC Architectures................................................................................148 6.4.1 Introduction .............................................................................148 6.4.2 Binary-Weighted Resistor DAC..............................................151 6.4.3 Binary-Weighted Current DAC...............................................152 6.4.4 R-2R Ladder DAC...................................................................152 6.4.5 Resistor String DAC................................................................153 6.4.6 Segmented Resistor String DAC .............................................153 6.4.7 Sigma-Delta (ΣΔ) DAC ...........................................................154 6.4.8 Hybrid DAC ............................................................................154 6.5 DAC Test ..............................................................................................155 xx Table of Contents 6.5.1 Introduction .............................................................................155 6.5.2 Static (DC) Tests .....................................................................155 6.5.3 Transfer Curve Tests ...............................................................156 6.5.4 Dynamic Tests .........................................................................158 6.5.5 FFT, SNR, SFDR and THD.....................................................159 6.6 ADC Architectures................................................................................159 6.6.1 Introduction .............................................................................159 6.6.2 Successive Approximation ADC.............................................161 6.6.3 Integrating (Single and Dual Slope) ADC...............................162 6.6.4 Flash ADC...............................................................................162 6.6.5 Sigma-Delta (ΣΔ) ADC ...........................................................163 6.7 ADC test................................................................................................163 6.7.1 Introduction .............................................................................163 6.7.2 Static (DC) and Transfer Curve Tests......................................164 6.7.3 Dynamic Tests .........................................................................166 6.7.4 FFT Test ..................................................................................166 6.7.5 Code Density (Histogram) Test ...............................................166 6.8 Future Directions...................................................................................168 6.9 Summary ...............................................................................................169 6.10 References.............................................................................................169 Exercises .........................................................................................................171 7 Input-Output Test .........................................................................................175 7.1 Introduction...........................................................................................175 7.2 Electrical Overstress and Electrostatic Discharge ................................178 7.3 Digital I/O Structures ............................................................................179 7.3.1 Introduction .............................................................................179 7.3.2 CMOS Inverter ........................................................................182 7.3.3 Logic Design Variants .............................................................186 7.3.4 TTL Family Variants ...............................................................186 7.3.5 CMOS Family Variants ...........................................................187 7.3.6 Digital Cell Schematics ...........................................................188 7.4 Digital I/O Test .....................................................................................188 7.4.1 Introduction .............................................................................188 7.4.2 Measuring Input Cell Voltage and Current..............................191 7.4.3 Measuring Output Cell Voltage and Current ...........................191 7.4.4 Dealing with Bidirectional Cells .............................................192 7.4.5 Dealing with Internal Pull-Ups and Pull-Downs .....................192 7.5 Analogue I/O Structures........................................................................192 7.6 Analogue I/O Test.................................................................................193 7.7 Future Directions...................................................................................193 7.8 Summary ...............................................................................................194 7.9 References.............................................................................................195 8 Design for Testability – Structured Test Approaches................................197 8.1 Introduction...........................................................................................197 8.2 Observability and Controllability..........................................................198 Table of Contents xxi 8.3 Digital DfT............................................................................................199 8.3.1 Design Partitioning ..................................................................199 8.3.2 Scan Path Test .........................................................................200 8.3.3 Built-In Self-Test (BIST).........................................................204 8.3.4 1149.1 Boundary Scan.............................................................208 8.3.5 P1500 Core Test Standard Development.................................212 8.4 Analogue and Mixed-Signal DfT..........................................................212 8.4.1 Overview .................................................................................212 8.4.2 1149.4 Mixed-Signal Test Bus ................................................215 8.5 Future Directions for DfT and BIST.....................................................217 8.6 Summary ...............................................................................................218 8.7 References.............................................................................................218 Exercises .........................................................................................................221 9 System on a Chip (SoC) Test ........................................................................225 9.1 Introduction...........................................................................................225 9.2 Examples of SoC Devices.....................................................................228 9.3 Test Complexity and Additional Problems ...........................................228 9.4 P1500 Core Test Standard Development ..............................................229 9.5 Future Directions for SoC Test .............................................................230 9.6 Summary ...............................................................................................231 9.7 References.............................................................................................232 10 Test Pattern Generation and Fault Simulation ..........................................235 10.1 Introduction ...........................................................................................235 10.2 Test Pattern Generation.........................................................................238 10.3 Digital Fault Simulation ........................................................................240 10.4 Analogue Fault Simulation....................................................................243 10.5 Mixed-Signal Fault Simulation .............................................................247 10.6 Issues with Fault Simulation .................................................................248 10.7 Circuit vs Behavioural Level Fault Simulation .....................................249 10.8 Future Directions...................................................................................249 10.9 Summary ...............................................................................................250 10.10 References .............................................................................................250 Exercises .........................................................................................................253 11 Automatic Test Equipment (ATE) and Production Test ...........................257 11.1 Introduction...........................................................................................257 11.2 Production Test Flow ............................................................................258 11.3 ATE Systems ........................................................................................260 11.4 Future Directions for ATE Systems ......................................................264 11.5 Summary ...............................................................................................265 11.6 References.............................................................................................265 12 Test Economics..............................................................................................267 12.1 Introduction...........................................................................................267 12.2 Purpose of a Test Economics Model.....................................................269 xxii Table of Contents 12.3 Test Economics Model Development ...................................................271 12.4 Summary ...............................................................................................273 12.5 References.............................................................................................274 Appendices A Introduction to VHDL..................................................................................275 A.1 Introduction...........................................................................................275 A.2 Entities and Architectures .....................................................................276 A.3 Libraries, Packages and Configurations................................................277 A.4 VHDL Testbench ..................................................................................277 A.5 References.............................................................................................278 B Introduction to Verilog®-HDL.....................................................................279 B.1 Introduction...........................................................................................279 B.2 Verilog®-HDL Modules........................................................................280 B.3 Verilog®-HDL Testfixture ....................................................................280 B.4 Data Types ............................................................................................280 B.5 Lexical Conventions .............................................................................281 B.6 Example ................................................................................................282 B.7 References.............................................................................................284 C Introduction to Spice.....................................................................................285 C.1 Introduction...........................................................................................285 C.2 Scope of Discussions ............................................................................286 C.3 Input File Format ..................................................................................286 C.4 Commenting the Input File ...................................................................287 C.5 Analyses................................................................................................288 C.6 Input Stimuli .........................................................................................288 C.7 Defining Components in Spice .............................................................289 C.8 Scale Factors in Spice ...........................................................................289 C.9 Dealing with Design Hierarchy.............................................................290 C.10 References.............................................................................................290 D Introduction to MATLAB® ..........................................................................291 D.1 Introduction...........................................................................................291 D.2 Interactive and Batch Modes.................................................................292 D.3 Scalar Variables and Arithmetic Operators...........................................293 D.4 Useful Commands.................................................................................293 D.5 Matrix Variables and Arithmetic Operators..........................................294 D.6 Signals and Results Plotting..................................................................294 D.7 References.............................................................................................296 E Hardware Experimentation .........................................................................297 E.1 Introduction...........................................................................................297 E.2 Generic Tester Arrangement .................................................................298 E.3 CPLD Based Logic and Memory Tester ...............................................300 Table of Contents xxiii E.4 References.............................................................................................302 F VHDL Simulation Examples........................................................................303 F.1 Introduction...........................................................................................303 F.2 2-Input Combinational Logic Circuit....................................................305 F.3 8-Input Priority Encoder .......................................................................308 F.4 3-Bit Binary Counter.............................................................................311 F.5 3-Bit Linear Feedback Shift Register (LFSR).......................................314 F.6 Simple 4 x 8-Bit ROM..........................................................................316 F.7 Simple 4 x 8-Bit RAM..........................................................................319 G HSPICE® Simulation Examples...................................................................323 G.1 Introduction...........................................................................................323 G.2 Series Resonant LCR Circuit ................................................................324 G.3 MOS Transistor Amplifier ....................................................................325 G.4 CMOS Inverter......................................................................................326 G.5 3-Bit DAC.............................................................................................327 H MATLAB® Simulation Examples ................................................................331 H.1 Introduction...........................................................................................331 H.2 DAC example........................................................................................332 H.3 ADC example........................................................................................335 I Journals, Conferences and Organisations...................................................341 Bibliography........................................................................................................345 Index ....................................................................................................................359 IntegratedCircuitTestEngineering.part1.rar(该附件已经被下载45次) |
| 1楼 |
又见飞刀 普通会员 积分：67 |
|
又见飞刀 普通会员 积分：67 |
|
price_tsai 普通会员 积分：60 |
|
funny2055 普通会员 积分：15 |
|
rzhonglee 普通会员 积分：186 |
|
sand_qin 普通会员 积分：46 |
|
 四有芯人 论坛版主 积分：9260 |
|
robbotpat 普通会员 积分：8 |
|
|
